Semiconductor device structure with adhesion-enhanced semiconductor die

ABSTRACT

A semiconductor die includes a substantially oxide-free metal layer on at least a portion of a surface thereof. The substantially oxide-free metal may enhance adhesion of a packaging material, or mold compound, to the semiconductor die, prevent the occurrence of voids or presence of moisture between the packaging material and the adjacent surface of the semiconductor die, or otherwise prevent delamination of the packaging material from the adjacent surface of the semiconductor die. The substantially oxide-free metal may be copper, palladium, another substantially oxide-free metal, or a combination of substantially oxide-free metals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/852,632,filed May 24, 2004, pending, which application is a continuation ofapplication Ser. No. 10/309,643, filed Dec. 3, 2002, now U.S. Pat. No.6,740,545, issued May 25, 2004, which is a continuation of applicationSer. No. 09/873,581, filed Jun. 4, 2001, now U.S. Pat. No. 6,489,186,issued Dec. 3, 2002, which is a continuation of application Ser. No.09/394,180, filed Sep. 10, 1999, now U.S. Pat. No. 6,316,292, issuedNov. 13, 2001, which is a continuation of application Ser. No.08/963,395, filed Nov. 3, 1997, now U.S. Pat. No. 6,066,514, issued May23, 2000, which is a divisional of application Ser. No. 08/731,793,filed Oct. 18, 1996, now U.S. Pat. No. 5,760,468, issued Jun. 2, 1998,which is a continuation of application Ser. No. 08/306,024, filed Sep.14, 1994, now U.S. Pat. No. 5,583,372, issued Dec. 10, 1996.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to a semiconductor die packagingtechnique and, more particularly, to a die having a metal layer backside for enhanced adhesion of the die in a Leads On Chip (LOC) packagesystem.

2. Background of Related Art

A semiconductor integrated circuit (IC) packaged device generallyincludes an IC chip (die) being connected to inner leads of a lead frameby wire bonds. The chip, wire bonds, and inner leads are completelyencapsulated (packaged) for protection with a substance, such asplastic. Outer leads communicate with the inner leads of the lead frame,but the outer leads typically remain exposed for mounting of thepackaged device to external circuitry, such as a printed circuit board.Conventionally, encapsulation occurs by a transfer molding techniquewherein the encapsulation substance is a thermoset epoxy molded aroundand to the die and lead frame and subsequently cured.

In a conventional IC packaged device, a semiconductor die is placed onand bonded to a center die paddle of a lead frame for support. Innerlead fingers of the lead frame approach the paddle but do not contact orcommunicate with the paddle. Rather, wire bonds communicate betweencontact pads on the die and the inner lead fingers of the lead frame byspanning the gap between the die and the fingers. The wire bonds allowfor the transmission of the electrical signals to and from the die andthe lead frame.

However, to shrink the conventional packaging requirements, techniquessuch as the Lead On Chip (LOC) method have been developed. The LOCtechnique disposes the inner lead fingers of a lead frame directly overthe die (or IC chip) rather than away from the die, and the lead framedoes not include a die paddle for supporting the die. Double-sidedadhesive insulating tape attaches the conductive lead fingers to the dieso that no gap exists between the die and lead fingers. Wire bondscommunicate between the contact pads on the die and the inner leadfingers which are disposed over the insulating tape directly over aportion of the die adjacent the die pads.

This LOC technique allows the entire packaging of the IC device to besmaller because the inner lead fingers are disposed directly over thedie rather than separate from the die. Similar to the LOC technique,other variations of using an adhesive tape for adhering lead fingersand, consequently, shrinking packaging requirements include a Tape UnderFrame technique and a Leads Under Die method.

Although IC packaging is minimized in each of these packaging techniquesthat uses an adhesive tape, other problems surface. One such problem inthe LOC technique is the difficulty of obtaining a good, solid adhesivebond between the die and the package. One reason a solid bond is notachieved is because the oxide on the silicon die substrate does not lenditself to uniform wetting, which is necessary for good adhesion with theliquid mold compound.

When a die does not bond well with the mold compound package,delamination may occur and the device may potentially be ruined duringthe manufacturing process or surface mount of the package. Sinceproduction environment areas retain a substantial humidity level toreduce static buildup, i.e., often about 50%, moisture absorbs into themold compound and can penetrate delaminated areas between the die andmold compound. When the moisture is converted to steam from heatprocesses and the steam pressure is greater than the strength of theadhesion couple between the mold compound and the die, the mold compoundwill crack or explode with a “popcorn” effect.

To overcome this potential package cracking problem, one technique hasbeen to bake the moisture out of the mold compound to ensure a lowmoisture content within the package. Another step is to place the devicein a “dry package” for shipping purposes by placing the finalsemiconductor chip product in a shipping container with a desiccantdrying agent, such as silica gel. Although these techniques are commonlyused in the semiconductor industry, they provide only a temporarysolution. Namely, when a semiconductor manufacturer ships a “dried”packaged device by following these techniques, the device may stillabsorb moisture at a customer's site after the device is removed fromthe shipping container materials. Furthermore, if the die hasdelaminated even slightly, the package is subject to moisturepenetration again and the package may subsequently crack if exposed tosufficient heat.

Another technique for reducing delamination potential is disclosed inU.S. Pat. No. 5,227,661 issued to Heinen on Jul. 13, 1993. Although thismethod provides a working solution, it retains disadvantages by its useof aminopropyltriethox-silane as a coating on the die.

Obviously, the foregoing problems and solutions associated withproviding a good bond between a die and a die package to avoiddelamination and cracking of the package are undesirable aspects ofconventional semiconductor packaging techniques. Accordingly, objects ofthe present invention are to provide an improved bonding between asemiconductor die and its encapsulating package in order to decreasedelamination potential of the die from the package.

SUMMARY OF THE INVENTION

According to principles of the present invention in its preferredembodiment, a back side of a semiconductor die includes a metal layerdeposited thereon for enhancing adhesion between the die and a moldcompound package. The metal layer is substantially oxide free. The dieis coated with a layer or layers of copper (Cu) and/or palladium (Pd) byelectroplating or electroless coating techniques.

According to further principles of the present invention, the metallayer preferably comprises approximately 50 micro inches of a Cu layerdeposited over the back side of the die and approximately 2 to 3 microinches of a Pd layer deposited over the Cu layer.

Advantageously, the metal layer on the die provides a uniform wettingsurface for better adhesion of the die with the mold compound duringencapsulation. The increased adhesion reduces delamination potential ofthe die from the package and, consequently, reduces cracking of thepackage.

The aforementioned principles of the present invention provide anadhesion enhanced semiconductor die for improving adhesion of the diewith a mold compound packaging. Other objects, advantages, andcapabilities of the present invention will become more apparent as thedescription proceeds.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is an end-section view of a packaged integrated circuit diehaving the present invention adhesion enhanced layer deposited thereon;and

FIG. 2 is an enlarged partial view of FIG. 1 showing a corner edge ofthe die and its adhesion enhanced layer.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is an end-section view of packaged integrated circuit (IC) 10.Lead frame 15 is disposed over IC die 20, the lead frame including innerand outer lead finger portions 25 and 30, respectively. Inner leadfinger portions 25 are adjacent die pads 35, and outer lead fingerportions 30 extend outward of mold compound packaging 40 for connectionwith appropriate external circuitry.

Insulator adhesive tape strips 45 are disposed between inner lead fingerportions 25 and frontside 50 of die 20 to adhere the lead fingerportions to the die. Integrated circuitry is disposed on frontside 50 ofdie 20. Wire bonds 52 communicate between inner lead finger portions 25and die pads 35 for making the electrical connection between the die andthe lead finger portions.

Metal layer 55 is shown deposited over back side 60 of die 20. Metallayer 55 enhances adhesion of die 20 with mold compound packaging 40.Metal layer 55 is deposited over die 20 using an electroplating processor electroless coating process well known in the art prior to packagingthe die with mold compound packaging 40.

Metal layer 55 provides a uniform wetting surface for mold compoundpackaging 40 to adhere better to die 20. Although shown in its hardenedand cured state, mold compound packaging 40 is in a flowing state whenit is initially heated over and molded around die 20. Consequently, theuniform wetting surface provided by metal layer 55 enhances the adhesionbetween the die and the mold compound packaging.

In its preferred embodiment, metal layer 55 is substantially oxide free.Also, preferably, the metal layer is either palladium (Pd) or copper(Cu), or a combination thereof, although it is obvious other metals maylikewise suffice. Although copper is cheaper in cost, it retains moreoxide which counteracts the intended adhesion. Palladium is moreexpensive, but provides a substantially oxide-free layer foreffectuating a good bond with the mold compound.

Although a single metal layer suffices to provide the advantages of thepresent invention, in its preferred embodiment, metal layer 55 actuallycomprises a plurality of layers as shown in FIG. 2. Namely, a cheaper,thicker layer 65 of copper deposited over back side 60 of die 20provides a good barrier to the oxide on die 20. A thinner layer 70 ofpalladium is deposited over the copper layer 65 to provide an even moreuniform wetting surface. The palladium is also substantially free fromoxide. Preferably, about 50 micro inches of copper and approximately 2to 3 micro inches of palladium are deposited. Consequently, thiscombination of metal layers provides the enhanced adhesion metal layer55 on die 20 and provides a good balance of cost and effectiveness.

As previously mentioned, when a die does not bond well with the moldcompound package, delamination may occur and the device may potentiallybe ruined during the manufacturing process or surface mount of thepackage because of moisture penetration between the die and compound.When the moisture is converted to steam from heat processes and thesteam pressure is greater than the strength of the adhesion coupledbetween the mold compound packaging and the die, the mold compoundpackaging will crack or explode with a “popcorn” effect.

The present invention, as described and diagramed, reduces thispotential package cracking problem. Consequently, no baking of themoisture out of the mold compound packaging is needed, and no “drypackaging” the device for shipping purposes is needed.

What has been described above are the preferred embodiments for asemiconductor die having a metal layer back side for enhancing adhesionbetween the die and its mold compound packaging. It is clear that thepresent invention provides a powerful tool for reducing delaminationpotential of a die and subsequent cracking of the mold compoundpackaging. While the present invention has been described by referenceto specific embodiments, it will be apparent that other alternativeembodiments and methods of implementation or modification may beemployed without departing from the true spirit and scope of theinvention.

1. A semiconductor device configured for enhanced adhesion to packagingmaterial comprising: a semiconductor die with a back side; at least onesubstantially oxide-free metal in contact with at least a portion of theback side; and packaging material adjacent to at least a portion of theat least one substantially oxide-free metal.
 2. The semiconductor deviceof claim 1, further comprising: leads secured in place relative to aremainder of the semiconductor device.
 3. The semiconductor device ofclaim 2, wherein the leads are secured directly to the remainder of thesemiconductor device in a leads-over-chip arrangement.
 4. Thesemiconductor device of claim 1, wherein the packaging materialcomprises a plastic molding material.
 5. The semiconductor device ofclaim 4, wherein the plastic molding material comprises a thermosetepoxy material.
 6. The semiconductor device of claim 1, wherein the atleast one substantially oxide-free metal comprises palladium or copper.7. The semiconductor device of claim 1, wherein the at least onesubstantially oxide-free metal comprises a plurality of metals.
 8. Thesemiconductor device of claim 7, wherein the plurality of metalscomprises copper in contact with the back side.
 9. The semiconductordevice of claim 8, wherein the copper has a thickness of approximately50 micro inches.
 10. The semiconductor device of claim 8, wherein theplurality of metals comprises palladium in contact with the copper. 11.The semiconductor device of claim 10, wherein the palladium alsocontacts the packaging material.
 12. The semiconductor device of claim10, wherein the palladium has a thickness of approximately 2 to 3 microinches.
 13. A semiconductor device structure, comprising: asemiconductor die with a back side; an adhesion-enhancing layercomprising at least one substantially oxide-free metal contacting theback side; and packaging material contacting the at least onesubstantially oxide-free metal with substantially no voids located ormoisture trapped between an entire extent of an interface between thesubstantially oxide-free metal and the packaging material.
 14. Thesemiconductor device structure of claim 13, wherein the substantiallyoxide-free metal comprises copper or palladium.
 15. The semiconductordevice structure of claim 14, wherein the substantially oxide-free metalcomprises copper having a thickness of approximately 50 micro inches.16. The semiconductor device structure of claim 14, wherein thesubstantially oxide-free metal comprises palladium having a thickness ofapproximately 2 to 3 micro inches.
 17. The semiconductor devicestructure of claim 15, wherein the substantially oxide-free metalcomprises copper and palladium.
 18. The semiconductor device structureof claim 17, wherein the copper contacts the back side of thesemiconductor die.
 19. The semiconductor device structure of claim 18,wherein the palladium contacts the copper.
 20. The semiconductor devicestructure of claim 19, wherein the palladium contacts the packagingmaterial.